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GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number
IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( IF 2.8 ) Pub Date : 2020-01-01 , DOI: 10.1109/tvlsi.2019.2959847
Yuxuan Wang , Yuanyong Luo , Zhongfeng Wang , Qinghong Shen , Hongbing Pan

This article presents hardware implementation for computing arbitrary roots of a single-precision floating-point number. The proposed architecture is based on Generalized Hyperbolic COordinate Rotation Digital Computer (GH CORDIC) algorithm. Benefiting from the wide range of floating-point numbers, our design is able to compute the Nth root (N ≥ 2) of a single-precision floating-point number. After implementation, a series of tests have been carried out, including accuracy, power consumption, performance comparison, and so on. Simulation results indicate that our proposed method is capable of calculating the Nth root of a positive single-precision floating-point number with a relative error of 10-7 approximately and promises an error-flatten performance. Synthesized results from a design compiler under TSMC-40-nm CMOS technology show that our design can achieve the highest frequency of 2.38 GHz with the area consumption of 140894.44 μm2 and power consumption of 86.9573 mW.

中文翻译:


基于 GH CORDIC 的单精度浮点数 $N$ 次根计算架构



本文介绍了计算单精度浮点数任意根的硬件实现。所提出的架构基于广义双曲坐标旋转数字计算机(GH CORDIC)算法。受益于广泛的浮点数,我们的设计能够计算单精度浮点数的 N 次方根 (N ≥ 2)。实现后进行了一系列的测试,包括精度、功耗、性能对比等。仿真结果表明,我们提出的方法能够计算正单精度浮点数的 N 次根,相对误差约为 10-7,并具有误差平坦的性能。 TSMC-40-nm CMOS工艺下的设计编译器的综合结果表明,我们的设计可以实现最高频率2.38 GHz,面积消耗为140894.44 μm2,功耗为86.9573 mW。
更新日期:2020-01-01
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