Unlike central processing units (CPUs), field-programmable gate arrays (FPGAs) have conventionally been powered with a fixed supply voltage ( $V_{\text {dd}}$ ). However, recent efforts have shown that adopting dynamic voltage scaling reduces FPGA power consumption significantly. In this article, we analyze the delay sensitivity of different FPGA circuit elements to supply voltage changes and determine that conventional lookup table (LUT) designs greatly impact variable ${V_{\text {dd}}}$ operation. To build FPGAs with lower delay sensitivity to ${V_{\text {dd}}}$ , we propose several new LUT designs, including gate boosting the LUT, decoding the slowest two inputs of the LUT, and using separate voltage islands for the FPGA LUTs and routing. Our fastest proposed design (decode-driver island) reduces the area-delay product of the FPGA logic plus routing tile compared to a conventional design by 12% and 52% at ${V_{\text {dd}}}$ values of 0.8 V (the nominal voltage) and 0.6 V, respectively. Since our proposed FPGA tile designs are faster and have lower delay sensitivity to voltage, they offer better ${\text {Energy-Delay} {{^{\mathrm{ 2}}}}}$ product ( ${\text {ED} {{^{\mathrm{ 2}}}}}$ ) than that of the baseline at nominal ${V_{\text {dd}}}$ and below. Our decode-driver-island FPGA achieves a 26% ${\text {ED} {{^{\mathrm{ 2}}}}}$ reduction over the conventional design at the most efficient ${\text {ED} {{^{\mathrm{ 2}}}}}$ operating point.

中文翻译：

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优化可变电压电源的 FPGA 逻辑电路

与中央处理单元 (CPU) 不同，现场可编程门阵列 (FPGA) 通常采用固定电源电压 ( $V_{\text {dd}}$ ）。然而，最近的努力表明，采用动态电压缩放可显着降低 FPGA 功耗。在本文中，我们分析了不同 FPGA 电路元件对电源电压变化的延迟敏感性，并确定传统的查找表 (LUT) 设计极大地影响变量 ${V_{\text {dd}}}$ 手术。构建对延迟敏感度较低的 FPGA ${V_{\text {dd}}}$ ，我们提出了几种新的 LUT 设计，包括门升压 LUT、解码 LUT 最慢的两个输入，以及为 FPGA LUT 和路由使用单独的电压岛。与传统设计相比，我们提出的最快设计（解码驱动器岛）将 FPGA 逻辑加布线块的面积延迟乘积减少了 12% 和 52% ${V_{\text {dd}}}$ 值分别为 0.8 V（标称电压）和 0.6 V。由于我们提出的 FPGA tile 设计速度更快，对电压的延迟敏感性更低，因此它们提供了更好的 ${\text {能量延迟} {{^{\mathrm{ 2}}}}}$ 产品 （ ${\text {ED} {{^{\mathrm{ 2}}}}}$ ) 比名义上的基线 ${V_{\text {dd}}}$ 和下面。我们的解码驱动器岛 FPGA 实现了 26% ${\text {ED} {{^{\mathrm{ 2}}}}}$ 以最有效的方式减少传统设计 ${\text {ED} {{^{\mathrm{ 2}}}}}$ 操作点。