An extremely high-resolution, 2-D Vernier field-programmable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is limited to less than 20 ns. To achieve both high-precision phase division and wide measurement range, a phase-locked loop (PLL)-based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this article. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For a concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6-ps resolution. The differential nonlinearity (DNL), integral nonlinearity (INL), and rms resolution are measured to be merely −0.157 to 0.137 LSB, −0.176 to 0.184 LSB, and 1.0 LSB, which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high-precision phase division technique can be applied to not only the TDC but also the digital-to-time converter (DTC) to enrich its future applications.

中文翻译：

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具有超频和双倍数据速率的高精度 PLL 延迟矩阵，用于精确的 FPGA 时间数字转换器

最近提出了一种具有相位缠绕和平均的极高分辨率、二维游标现场可编程门阵列 (FPGA) 时间数字转换器 (TDC)，以获得 2.5 ps 的极精细分辨率。然而，延迟矩阵中的单元延迟没有得到完全控制，因此 TDC 性能在很大程度上取决于单元延迟的随机分布，并且输入范围被限制在 20 ns 以下。为了同时实现高精度分相和宽测量范围，本文提出了一种基于锁相环 (PLL) 的延迟矩阵，它能够超频和双倍数据速率 (DDR)。所有延迟单元都在 PLL 的精确控制下，以生成在参考时钟周期内均匀划分的输出相位。对于概念证明，TDC 架构在 Altera Stratix-IV FPGA 芯片上实现，以实现 15.6 ps 的分辨率。微分非线性 (DNL)、积分非线性 (INL) 和 rms 分辨率经测量仅为 -0.157 至 0.137 LSB、-0.176 至 0.184 LSB 和 1.0 LSB，这证明了所提出的结构优于其随机对应结构。所提出的高精度分相技术不仅可以应用于 TDC，还可以应用于数字时间转换器 (DTC)，以丰富其未来的应用。