This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10−7). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm2, power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm2 and 10.2 pJ/bit, respectively.

中文翻译：

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基于降低复杂度的第二最小近似最小和算法的 75-Gb/s/mm² 和高能效 LDPC 解码器

本文提出了一种基于新颖的第二最小近似最小和 (SAMS) 算法的高吞吐量和低路由复杂度的低密度奇偶校验 (LDPC) 解码器设计。通过减少路由网络关键路径中所需的互连，可以缓解路由拥塞。使用 28-nm 1P9M CMOS 工艺的实施和布局后结果表明，所提出的设计可以为毫米波 60-GHz 基带系统实现 10.5 Gb/s 的吞吐量，同时满足低误码率 (BER) 要求 (10− 7）。与传统的 min-sum (MS) 和归一化 MS (NMS) 算法相比，所提出的设计将路由网络中的布线减少了 21%，并将面积提高了 12%。通过考虑基于实际基带系统的 BER 和信噪比 (SNR) 要求的内部消息传递分辨率，可以获得额外的硬件优化。通过使用共享地址生成器来有效降低功耗，该生成器利用并行度来减少一组存储元件上的切换活动。LDPC 解码器的核心面积为 0.14 mm2，312.5 MHz 时的功耗为 81 mW，面积和功率效率分别为 75 Gb/s/mm2 和 10.2 pJ/bit。