Silicon debugging is carried out in multiple sessions which are characterized by run-and-halt intervals. One of the important criteria for the success of this method is that the debugging infrastructure should capture only the erroneous data which can add important insights to the debugging process. However, identification of such suspect clock cycles is not a trivial exercise and requires an systematic approach. We propose a debugging architecture for enhancing the multisession procedure using the technique of on-chip debug data compression. The first session assists in identifying those erroneous clock cycles, and the useful debug data are collected in the second session with the help of markers called tag bits. At the cost of a minimal increase in area overhead, the proposed architecture achieves finer temporal visibility expansion because of the debug data collection in a segregated manner. During the offline analysis of the collected debug data, error localization can be achieved to a finer resolution. We evaluate our methodology on several designs for different kinds of error configurations. Experimental results show that the proposed methodology can achieve better on-chip storage utilization and the expansion in the temporal observation window compared to similar techniques in the literature.

中文翻译：

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在多会话硅调试期间捕获细粒度内部可见性的方法

硅调试是在多个会话中进行的，这些会话的特点是运行和暂停间隔。这种方法成功的重要标准之一是调试基础设施应该只捕获错误数据，这些数据可以为调试过程增加重要的洞察力。然而，识别此类可疑时钟周期并非易事，需要系统的方法。我们提出了一种调试架构，用于使用片上调试数据压缩技术增强多会话过程。第一个会话帮助识别那些错误的时钟周期，在第二个会话中借助称为标记位的标记收集有用的调试数据。以最小的面积开销增加为代价，由于以隔离的方式收集调试数据，所提出的架构实现了更精细的时间可见性扩展。在对收集到的调试数据进行离线分析时，可以实现更精细的错误定位。我们针对不同类型的错误配置评估了几种设计的方法。实验结果表明，与文献中的类似技术相比，所提出的方法可以实现更好的片上存储利用率和时间观察窗口的扩展。