This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches.

中文翻译：

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使用成对比较器对流水线 SAR ADC 中的位权重进行背景校准

本简介介绍了一种用于流水线逐次逼近寄存器（流水线 SAR）模数转换器 (ADC) 的背景校准技术，该技术可解决电容器不匹配和不准确的级间增益误差引起的误差。抖动信号被注入电容数模转换器 (DAC)，而其残余电压增量则通过具有相反极性偏移的成对比较器中和，从而放宽了残余放大器的设计要求。当其中一个比较器产生残留信号时，另一个比较器检测信号范围并帮助获得位权重。本简介还介绍了具有相反偏移量的成对比较器的电路设计。背景校准技术在 5b + 8b 流水线 SAR ADC 中得到验证。仿真结果表明，无杂散动态范围 (SFDR) 和信噪比和失真比 (SNDR) 分别从 54.5 提高到 94 dB 和 49 到 68.9 dB。电压摆幅增量的平均值为 34 mV，包括噪声源、偏移、增益误差和电容器失配。