In this brief, a pMOS pass gate (PPG) local bitline static random access memory (LB SRAM) architecture is proposed to reduce the read delay and resolve the half-select issue with a small area overhead. Virtual VSS write assist is included in the architecture to improve write ability. In 22-nm fin-shaped FET (FinFET) technology, the proposed PPG LB architecture achieves an improved read delay and reduced total operation energy by 44% and 65%, respectively, at 0.4 V, compared to the full-swing LB (FSLB) SRAM architecture.

中文翻译：

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pMOS 通门本地位线 SRAM 架构，具有用于近阈值操作的虚拟 $V_{\mathrm{SS}}$


本文提出了一种 pMOS 传输门 (PPG) 局部位线静态随机存取存储器 (LB SRAM) 架构，以减少读取延迟并以较小的面积开销解决半选择问题。架构中包含虚拟VSS写入辅助，以提高写入能力。在 22 nm 鳍状 FET (FinFET) 技术中，与全摆幅 LB (FSLB) 相比，所提出的 PPG LB 架构在 0.4 V 电压下实现了改进的读取延迟并将总操作能量分别降低了 44% 和 65% ) SRAM 架构。