Conventional radiation-hardened cells of static random access memory (SRAM) are not robust enough in 28 nm technology, due to partial immunity of single-event upset (SEU) effect (Quatro-based cells) or insufficient critical charges in sensitive nodes (conventional stacked cells). The reduction of read noise margin (RNM) at the low supply voltage (VDD) confines these cells from low VDD applications. We propose a novel interleaving stacked-14T (ILS-14T) cell which prevents voltage transient from propagating to other redundancies. The ILS-14T cell can be resilient to both 0-1 and 1-0 upsets by injecting 12 mA in sensitive nodes. The critical charges of the ILS-14T cell are substantially larger than most other hardened cells at VDD from 0.3 to 0.9 V. The RNM of the ILS-14T cell is two times of most Quatro-based cells at 0.3 V VDD and larger than most cells at 0.6 and 0.9 V VDD. The area of occupation is 334% of the conventional 6T cell, which equals other 14T cells. The static-dynamic decoder array with 20%-40% area penalty and 116%-132% delay of rising edge, when compared with the conventional one, reduces the read failure rate by preventing single event transients (SETs) from propagating to unexpected word lines (WLs).

中文翻译：

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适用于空间应用、采用 28 nm 技术的抗辐射 0.3-0.9V 电压可扩展 14T SRAM 和外围电路


静态随机存取存储器 (SRAM) 的传统抗辐射单元在 28 nm 技术中不够稳健，原因是单粒子翻转 (SEU) 效应（基于 Quatro 的单元）的部分免疫力或敏感节点中关键电荷不足（传统的堆叠单元）。低电源电压 (VDD) 下读取噪声容限 (RNM) 的降低限制了这些单元在低 VDD 应用中的应用。我们提出了一种新型交错堆叠 14T (ILS-14T) 电池，可防止电压瞬变传播到其他冗余。通过在敏感节点中注入 12 mA 电流，ILS-14T 单元可以对 0-1 和 1-0 扰动具有弹性。在 VDD 为 0.3 至 0.9 V 时，ILS-14T 单元的临界电荷明显大于大多数其他硬化单元。在 0.3 V VDD 时，ILS-14T 单元的 RNM 是大多数基于 Quatro 的单元的两倍，并且大于大多数基于 Quatro 的单元。电池电压为 0.6 和 0.9 V VDD。占用面积是传统6T电池的334%，与其他14T电池持平。与传统解码器阵列相比，静态-动态解码器阵列具有20%-40%的面积损失和116%-132%的上升沿延迟，通过防止单事件瞬态（SET）传播到意外字来降低读取失败率线 (WL)。