Among other uses, oversampling can be useful for systems that aim to accurately estimate the time delay between two signals. Due to the simplicity of its implementation, $$\varSigma \varDelta $$ Σ Δ analog-to-digital converters have been largely used when oversampled signals are required. In this work, two methods for parallel evaluation of the discrete Fourier transform (DFT) of $$\varSigma \varDelta $$ Σ Δ signals are presented, targeting frequency domain analysis of oversampled signals. The basic proposed method relies on the partial storage of DFT outputs in memories, considering binary inputs and using a technique named bitstream decomposition to reduce the dimensionality. Additionally, the basic method has been combined to the Cooley–Tukey algorithm to derive a more efficient method. When compared to conventional strategies to compute partial DFTs sequentially, the proposed methods had shown similar results, using feasible memory resources. However, the method allows highly parallel implementations with linear increase in performance as new processing units are added. It has been shown that its implementation on FPGA not only may improve performance but may also reduce memory utilization in more than 80%, enabling low resource FPGAs to compute the FFT of oversampled $$\varSigma \varDelta $$ Σ Δ sequences.

中文翻译：

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一种面向 FPGA 的 Sigma-Delta 信号 FFT 算法

除其他用途外，过采样对于旨在准确估计两个信号之间的时间延迟的系统非常有用。由于其实现的简单性，$$\varSigma \varDelta $$ Σ Δ 模数转换器在需要过采样信号时已被大量使用。在这项工作中，提出了两种并行评估 $$\varSigma \varDelta $$ Σ Δ 信号的离散傅立叶变换 (DFT) 的方法，针对过采样信号的频域分析。所提出的基本方法依赖于内存中 DFT 输出的部分存储，考虑二进制输入并使用称为比特流分解的技术来降低维度。此外，基本方法已与 Cooley-Tukey 算法相结合，以推导出更有效的方法。与顺序计算部分 DFT 的传统策略相比，所提出的方法显示出类似的结果，使用可行的内存资源。然而，随着新处理单元的添加，该方法允许在性能线性增加的情况下进行高度并行的实现。已经表明，它在 FPGA 上的实现不仅可以提高性能，还可以将内存利用率降低 80% 以上，使低资源 FPGA 能够计算过采样的 $$\varSigma \varDelta $$ Σ Δ 序列的 FFT。