Physically unclonable functions (PUF) are digital fingerprints which generate high entropy, temper-resilient keys and/or chip-identifiers for security applications. When considering the miniaturized hardware development for the Internet of Things (IoT), security is of high importance. In this case, PUF designing using SRAM or D flip-flops are quite common but with compromised uniqueness due to the limited silicon area. In this work, a symmetric tri-state D flip-flop based lightweight PUF is proposed with increased uniqueness. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers a uniqueness of 0.4994, which is the highest among all the considered architectures. Compared to the Arbiter PUF the proposed architecture has 0.267 \(\times\), 0.064 \(\times\), and 0.043 \(\times\) less, power, silicon area, and energy per bit, respectively. Similarly, when compared with the Ring Oscillator PUF, the proposed architecture has 0.017 \(\times\), 0.031 \(\times\), and 0.0005 \(\times\) less, power, silicon area, and energy per bit, respectively. Also, unlike other flip-flop based PUF, the proposed one does not require any post-processing block to remove the bias, thus contributes to saving the total implementation area and power of the system. An FPGA implementation is also presented as a proof-of-concept to verify functional correctness. For a better performance comparison among the considered architectures, a novel figure of merit (FOM) considering power, reliability, delay, silicon area, and uniqueness has been proposed, and it is observed that the proposed architecture offers the highest FOM among considered PUF architectures.

物理上不可克隆的功能（PUF）是数字指纹，可为安全应用生成高熵，具有回弹力的密钥和/或芯片标识符。在考虑物联网（IoT）的微型硬件开发时，安全性至关重要。在这种情况下，使用SRAM或D触发器进行PUF设计非常普遍，但由于硅面积有限，其独特性受到了损害。在这项工作中，提出了一种基于对称三态D触发器的轻量级PUF，具有增强的唯一性。所建议的体系结构是使用标准的40 nm CMOS技术实现的。布局后的仿真结果表明它具有0.4994的唯一性，在所有考虑的体系结构中是最高的。与Arbiter PUF相比，建议的体系结构为0.267  \（\ times \），分别减少0.064  \（\ times \）和0.043  \（\ times \），功率，硅面积和每位能量。同样，与环形振荡器PUF相比，建议的体系结构具有0.017  \（\ times \），0.031  \（\ times \）和0.0005  \（\ times \）功耗，硅面积和每位能量分别更少。而且，与其他基于触发器的PUF不同，所提出的PUF不需要任何后处理块即可消除偏差，从而有助于节省整个实施面积和系统功耗。FPGA实现也作为验证功能正确性的概念验证而提出。为了在考虑的架构之间进行更好的性能比较，提出了一种考虑功率，可靠性，延迟，硅面积和唯一性的新型品质因数（FOM），并且观察到，所提出的架构在考虑的PUF架构中提供了最高的FOM。 。