In this paper, a variable-size power-efficient two-parallel prime factor MDC FFT architecture is proposed which uses a novel reconfigurable processing element pair (RPEP). The prior reconfigurable FFT approaches merely concentrate on FFT architectures with a wide range of FFT sizes. The processing elements/stages are connected to or disconnected from the architecture to vary the size of the FFT. As a result, the hardware is underutilized when the processing elements are disconnected (unused). In the proposed approach, power reduction and effective utilization of hardware are concentrated rather than increasing the number of FFT sizes. The proposed RPEP structure contains two two-parallel processing element which can be either connected in serial or parallel. If one of the processing elements in the RPEP must be disconnected to reduce the FFT size, then the two two-parallel processing elements in the RPEP are configured as a single four-parallel processing element. Due to parallel processing, the frequency of operation is reduced by half and dynamic power is also reduced significantly. The architecture is designed in UMC 65 nm technology and can be configured in seventeen sizes ranging from 8 to 2048-points. The design occupies 0.67 mm.sq and consumption 17.74 mW power when operated at 100 MHz.

在本文中，提出了一种使用新型可重构处理元件对（RPEP）的可变大小，高能效的双并行素数MDC FFT架构。先前的可重构FFT方法仅集中于具有各种FFT大小的FFT体系结构。处理元件/级连接到体系结构或从体系结构断开以改变FFT的大小。结果，当处理元件被断开（未使用）时，硬件未被充分利用。在所提出的方法中，功率降低和硬件的有效利用被集中而不是增加FFT大小的数量。提出的RPEP结构包含两个两个并行处理元素，可以串联或并行连接。如果必须断开RPEP中的一个处理元素以减小FFT大小，然后将RPEP中的两个两个并行处理元素配置为单个四个并行处理元素。由于并行处理，操作频率降低了一半，动态功率也大大降低了。该架构采用UMC 65 nm技术设计，可以配置为17种大小，范围从8点到2048点。在100 MHz下工作时，该设计占地0.67 mm.sq，消耗功率17.74 mW。