The iMemComp (Intelligent memristive computing) gates are a family of logic gates based on the RRAM (Resistive Random Access Memory) devices. It has potential advantage for the design of high-performance logic circuits, because the iMemComp NAND, AND, NOT, and transmission gates only consume single cycle, respectively. However, the original two-input iMemComp OR gate, which requires three cycles, is a relatively slow gate. It decreases the performance of some logic circuits. This work proposes an improved iMemComp OR gate with only one cycle and three RRAM cells. Both the circuit performance and area consumption of the full-adder and LFSR circuits are improved by the application of the proposed OR gate. Furthermore, we propose a general synthesis method of logic circuits based on the improved logic gate. The synthesis results show that the circuits generated from the proposed synthesis method outperform the previous RRAM based counterparts for most cases of the MCNC benchmark circuits.

中文翻译：

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一种改进的 iMemComp 或门及其在逻辑电路中的应用

iMemComp（智能忆阻计算）门是一系列基于 RRAM（电阻式随机存取存储器）设备的逻辑门。它对于高性能逻辑电路的设计具有潜在优势，因为 iMemComp NAND、AND、NOT 和传输门分别只消耗单个周期。但是，原始的两输入 iMemComp OR 门需要三个周期，是一个相对较慢的门。它降低了一些逻辑电路的性能。这项工作提出了一种改进的 iMemComp OR 门，只有一个周期和三个 RRAM 单元。全加器和 LFSR 电路的电路性能和面积消耗都通过所提出的或门的应用得到改善。此外，我们提出了一种基于改进逻辑门的逻辑电路的通用综合方法。