A novel trench shielded planar gate IGBT (TSPG-IGBT) with self-biased pMOS is proposed in this paper. It features a P-layer beneath the trench of the TSPG-IGBT to form a self-biased pMOS, which provides an additional path for the hole current and clamps the potential of the nMOS’s intrinsic drain for lower saturation current. In the off-state, with the increasing potential of the N-cs (N-doped carrier store layer), the self-biased pMOS turns on and the potential of the P-layer will be clamped by the hole channel. Then, the reverse voltage is sustained by the P-layer/N-drift junction and the potential of the N-cs is shielded by the clamped P-layer region. Therefore, the N-cs can be heavily doped to reduce the on-state voltage ( ${V} _{\mathrm{ on}}$ ) without decreasing the breakdown voltage. Compared with the conventional TSPG-IGBT, the ${V} _{\mathrm{ on}}$ of the proposed TSPG-IGBT is reduced by 0.3 V at the current density of 200 A/cm² with the same turn-off loss. Besides, the saturation current density of the proposed one is decreased by 24%.

中文翻译：

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具有自偏置 pMOS 的沟槽屏蔽平面栅极 IGBT (TSPG-IGBT) 实现低导通电压和低饱和电流

本文提出了一种具有自偏置 pMOS 的新型沟槽屏蔽平面栅极 IGBT (TSPG-IGBT)。它的特点是在 TSPG-IGBT 的沟槽下方有一个 P 层，以形成自偏置 pMOS，为空穴电流提供额外的路径，并钳位 nMOS 本征漏极的电位以降低饱和电流。在关断状态下，随着N-cs（N掺杂载流子存储层）电位的增加，自偏置pMOS导通，P层的电位将被空穴沟道钳位。然后，反向电压由 P 层/N 漂移结承受，N-cs 的电位被钳位 P 层区域屏蔽。因此，可以重掺杂 N-cs 以降低导通电压（ ${V} _{\mathrm{ on}}$ ) 而不会降低击穿电压。与传统的 TSPG-IGBT 相比， ${V} _{\mathrm{ on}}$ 在 200 A/cm ²的电流密度下，所提出的 TSPG-IGBT 的电流密度降低了 0.3 V，同时关断损耗相同。此外，所提出的饱和电流密度降低了 24%。