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Schottky Barrier Height Engineering In β-Ga2O3 Using SiO2 Interlayer Dielectric
IEEE Journal of the Electron Devices Society ( IF 2.0 ) Pub Date : 2020-01-01 , DOI: 10.1109/jeds.2020.2974260
Arkka Bhattacharyya , Praneeth Ranga , Muad Saleh , Saurav Roy , Michael A. Scarpulla , Kelvin G. Lynn , Sriram Krishnamoorthy

This paper reports on the modulation of Schottky barrier heights (SBH) on three different orientations of $\beta $ -Ga2O3 by insertion of an ultra-thin SiO2 dielectric interlayer at the metal-semiconductor junction, which can potentially lower the Fermi-level pinning (FLP) effect due to metal-induced gap states (MIGS). Pt and Ni metal-semiconductor (MS) and metal-interlayer-semiconductor (MIS) Schottky barrier diodes were fabricated on bulk n-type doped $\beta $ -Ga2O3 single crystal substrates along the (010), (−201) and (100) orientations and were characterized by room temperature current-voltage (I-V) and capacitance-voltage (C-V) measurements. Pt MIS diodes exhibited 0.53 eV and 0.37 eV increment in SBH along the (010) and (−201) orientations respectively as compared to their respective MS counterparts. The highest SBH of 1.81 eV was achieved on the (010)-oriented MIS SBD using Pt metal. The MIS SBDs on (100)-oriented substrates exhibited a dramatic increment ( $> 1.5\times $ ) in SBH as well as reduction in reverse leakage current. The use of thin dielectric interlayers can be an efficient experimental method to modulate SBH of metal/Ga2O3 junctions.

中文翻译:

使用 SiO2 层间电介质在 β-Ga2O3 中进行肖特基势垒高度工程

本文报告了肖特基势垒高度 (SBH) 在三个不同方向上的调制 $\beta $ -Ga 2 O 3通过在金属-半导体结处插入超薄 SiO 2介电夹层,这可能会降低由于金属诱导间隙态 (MIGS) 引起的费米能级钉扎 (FLP) 效应。Pt 和 Ni 金属半导体 (MS) 和金属夹层半导体 (MIS) 肖特基势垒二极管在块体 n 型掺杂上制造 $\beta $ -Ga 2 O 3单晶衬底沿(010)、(-201)和(100)取向,并通过室温电流-电压(IV)和电容-电压(CV)测量表征。与其各自的 MS 对应物相比,Pt MIS 二极管在沿 (010) 和 (-201) 方向的 SBH 中分别表现出 0.53 eV 和 0.37 eV 增量。在使用 Pt 金属的 (010) 取向 MIS SBD 上实现了 1.81 eV 的最高 SBH。(100) 取向基板上的 MIS SBD 表现出显着的增加 ( $> 1.5\times $ ) 在 SBH 以及减少反向漏电流。薄介电夹层的使用可以是调制金属/Ga 2 O 3结的SBH的有效实验方法。
更新日期:2020-01-01
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