This work presents a novel general compact model for 7-nm technology node devices like FinFETs as an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects. The general compact model exhibits efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control electrostatic discharge (ESD) power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for path-finding researches on 5-nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

中文翻译：

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从器件角度及其他角度进行 7 纳米技术节点电路优化的新型通用紧凑模型方法

这项工作为 FinFET 等 7 纳米技术节点器件提供了一种新颖的通用紧凑模型，作为之前传统紧凑模型的扩展，该模型基于一些不太准确的元素，包括用于三维器件的一维泊松方程和用于短沟道效应的解析方程、量子效应和其他物理效应。通用紧凑模型具有提取效率高、精度高、缩放能力强、传输能力强等特点。作为演示应用程序，通过实施新提出的通用紧凑模型，系统地评估了 FinFET 的两个关键设计旋钮及其对 RC 控制静电放电 (ESD) 电源钳位电路的多重影响，包括器件设计、电路性能优化和变化控制. ESD 电源钳位的性能可以得到极大的提高。该框架也适用于 5 纳米节点环栅器件的寻路研究，如纳米线 (NW) FET、纳米片 (NSH) FET 等。