We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge_0.96Sn_0.04 nanowire MOSFETs (NWFETs) were simulated at a scaled gate length ( ${\mathrm{ L}}_{\mathrm{ G}}$ ) of 10 nm, using rigorous ballistic quantum transport simulations. To properly account for the non-parabolicity and anisotropy of the valence band, the $\text{k}\cdot \text{p}$ method was used. For each material, we simulated a set of six different transport/confinement directions, at a fixed OFF-state current ( ${\mathrm{ I}}_{\mathrm{ OFF}}$ ) of 100 nA/ $\mu \text{m}$ and supply voltage ${\mathrm{ V}}_{\mathrm{ DD}}=-0.5$ V to identify the direction with the highest ON-current ( ${\mathrm{ I}}_{\mathrm{ ON}}$ ). For Ge, GaSb, and GeSn [001]/110/ $\bar {1}10$ oriented NWFETs, with [001] being the direction of transport and 110, $\bar {1}10$ being the directions of confinement for the nanowire, showed the best ON-state performance, compared to other orientations. Our simulation results show that, despite having a higher percentage of SDT in OFF-state than silicon, GaSb [001]/110/ $\bar {1}10$ NWFET can outperform Si NWFETs. We further examined the role of doping in limiting SDT and demonstrated that the ON-state performance of Ge and GeSn NWFETs could be improved by reducing the doping in the source/drain (S/D) extension regions. Our simulation result show that with properly chosen channel transport orientation and S/D doping concentration, performance of materials with high hole mobility can be optimized to reduce the impact of SDT and provide a performance improvement over Si-channel based p-MOSFETs.

中文翻译：

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源漏隧道对 Si、Ge、GaSb 和 GeSn 纳米线 p-MOSFET 弹道性能的影响

我们研究了材料选择和方向在限制纳米线 (NW) p-MOSFET 中的源漏隧穿 (SDT) 方面的影响。Si、Ge、GaSb 和 Ge _0.96 Sn _0.04纳米线 MOSFET (NWFET) 在缩放栅极长度 ( ${\mathrm{ L}}_{\mathrm{ G}}$ ) 10 nm，使用严格的弹道量子传输模拟。为了正确解释价带的非抛物线和各向异性， $\text{k}\cdot \text{p}$ 方法被使用。对于每种材料，我们模拟了一组六个不同的传输/限制方向，在固定的关态电流（ ${\mathrm{ I}}_{\mathrm{ OFF}}$ ) 的 100 nA/ $\mu \text{m}$ 和电源电压 ${\mathrm{ V}}_{\mathrm{ DD}}=-0.5$ V 来识别具有最高导通电流的方向 ( ${\mathrm{ I}}_{\mathrm{ ON}}$ ）。对于 Ge、GaSb 和 GeSn [001]/110/ $\bar {1}10$ 定向 NWFET，[001] 是传输方向，110， $\bar {1}10$ 作为纳米线的限制方向，与其他方向相比，显示出最佳的导通状态性能。我们的模拟结果表明，尽管处于关断状态的 SDT 的百分比高于硅，但 GaSb [001]/110/ $\bar {1}10$ NWFET 的性能优于 Si NWFET。我们进一步研究了掺杂在限制 SDT 中的作用，并证明可以通过减少源极/漏极 (S/D) 扩展区的掺杂来改善 Ge 和 GeSn NWFET 的导通状态性能。我们的仿真结果表明，通过正确选择的信道传输方向和S / D掺杂浓度，可以优化具有高空穴迁移率的材料的性能，以减少SDT的影响，并提供基于SI沟道的P-MOSFET的性能改进。