Currently available quantum computing hardware platforms have limited 2-qubit connectivity among their addressable qubits. In order to run a generic quantum algorithm on such a platform, one has to transform the initial logical quantum circuit describing the algorithm into an equivalent one that obeys the connectivity restrictions. In this work we construct a circuit synthesis scheme that takes as input the qubit connectivity graph and a quantum circuit over the gate set generated by ##IMG## [http://ej.iop.org/images/2058-9565/5/2/025010/qstab79b1ieqn1.gif] {$\{\mathrm{CNOT},{R}_{Z}\}$} and outputs a circuit that respects the connectivity of the device. As a concrete application, we apply our techniques to Google’s Bristlecone 72-qubit quantum chip connectivity, IBM’s Tokyo 20-qubit quantum chip connectivity, and Rigetti’s Acorn 19-qubit quantum chip connectivity. In addition, we also compare the performance of our scheme as a function of sparseness of rand...

中文翻译：

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NISQ架构的量子电路优化

当前可用的量子计算硬件平台在其可寻址量子位之间具有有限的2量子位连接性。为了在这样的平台上运行一种通用量子算法，必须将描述该算法的初始逻辑量子电路转换为服从连接性限制的等效量子电路。在这项工作中，我们构建了一种电路综合方案，该方案以qubit连接图和由## IMG ## [http://ej.iop.org/images/2058-9565/5 /2/025010/qstab79b1ieqn1.gif] {$ \ {\ mathrm {CNOT}，{R} _ {Z} \} $}，并输出尊重设备连接性的电路。作为具体的应用，我们将技术应用于Google的Bristlecone 72量子位量子芯片连接，IBM的Tokyo 20量子位量子芯片连接，和Rigetti的Acorn 19量子位量子芯片连接性。此外，我们还比较了方案的性能与兰特稀疏度的关系。