In this paper, we present a methodology to characterize the I/O pins of a logic IC such as an application processor or ASIC with respect to soft-failure susceptibility due to electrostatic discharge. With the IC in a functional system, variable stress pulses are injected while the interface under test operates in real-world use cases. This test methodology enables the extraction of the IC behavior during ESD-like stress on a pin-by-pin basis. This characterization is intended to be performed during the validation stages of component development, making it possible to provide system developers with valuable information about potential modes of failure. This early detection of potential soft errors and their sensitivities can then be used to design for soft-failure robustness from the very beginning of system hardware and software design.

中文翻译：

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一种表征由于静电放电引起的集成电路上 I/O 软故障敏感性的系统方法

在本文中，我们提出了一种方法来表征逻辑 IC（例如应用处理器或 ASIC）的 I/O 引脚在静电放电引起的软故障敏感性方面的特性。借助功能系统中的 IC，当被测接口在实际用例中运行时，会注入可变应力脉冲。这种测试方法能够在逐个引脚的基础上提取类 ESD 应力期间的 IC 行为。此表征旨在在组件开发的验证阶段执行，从而可以为系统开发人员提供有关潜在故障模式的宝贵信息。这种对潜在软错误及其敏感性的早期检测可用于从系统硬件和软件设计的一开始就设计软故障鲁棒性。