This brief demonstrates the effectiveness of utilizing a 4-bit current steering digital to analog converter (DAC) as an adaptive power controller to adjust the dc quiescent current of a linear power amplifier as a function of the input signal power. A custom made metal-semiconductor field-effect transistor (MESFET), which is used as the amplifying transistor, and a current steering DAC have been integrated on the same substrate to minimize the power amplifier’s form factor and mismatches between the power tracker and the MESFET. This design has been implemented in a 45-nm CMOS SOI global foundries (GFs) process with a nominal supply voltage of 0.9 V and provides 31.8 dBm of output power, 45% peak efficiency and 24 dB maximum power gain. Measurement results at 70 MHz reveal about 10% efficiency improvement at 6-dB power back-off with continuous wave and 5% for standard 16-PSK EDGE modulated signals. The amplifier shows error vector magnitude of 5% and ACPR of −56.9 dBc at 400 kHz offset from the carrier frequency without digital pre-distortion, while transmitting 27 dBm of modulated output power.

中文翻译：

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使用电流调节对 CMOS SOI 中的瓦特级功率放大器进行自适应功率控制

本简介展示了利用 4 位电流控制数模转换器 (DAC) 作为自适应功率控制器来调整线性功率放大器的直流静态电流作为输入信号功率的函数的有效性。用作放大晶体管的定制金属半导体场效应晶体管 (MESFET) 和电流控制 DAC 已集成在同一基板上，以最大限度地减少功率放大器的外形尺寸以及功率跟踪器和 MESFET 之间的不匹配. 此设计采用 45 纳米 CMOS SOI 全球代工厂 (GF) 工艺实施，标称电源电压为 0.9 V，可提供 31.8 dBm 的输出功率、45% 的峰值效率和 24 dB 的最大功率增益。70 MHz 下的测量结果显示，在 6-dB 功率回退下，连续波效率提高了约 10%，标准 16-PSK EDGE 调制信号效率提高了 5%。放大器显示 5% 的误差矢量幅度和 -56.9 dBc 的 ACPR，在与载波频率的 400 kHz 偏移时没有数字预失真，同时传输 27 dBm 的调制输出功​​率。