This brief presents a 7-b 32-GS/s successive approximation register analog-to-digital converter (ADC) using a massive time-interleaving (TI) architecture. For low-skew multi-phase clocks, generation utilizing a delay-locked loop (DLL) phase-detector (PD) with a reduced offset is proposed to minimize skew between the clocks. Different clock path delays caused by distributed sub-ADCs over a large area in a massive TI-ADC are compensated for by multiplexing master clocks from the DLL. Offsets and skews in the sub-channels are calibrated on chip in the background via an additional dedicated sub-channel. A prototype chip was implemented in a 40-nm CMOS process with an active area of 0.36 mm2. The measured SFDR and SNDR of the prototype ADC at a conversion rate of 32 GS/s are 43.1 and 31.4 dB, respectively. The ADC, including the input buffers, consumes 125 mW under a single 0.9-V supply.

中文翻译：

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具有背景通道失配校准的 40-nm CMOS 7-b 32-GS/s SAR ADC

本简介介绍了使用大规模时间交织 (TI) 架构的 7-b 32-GS/s 逐次逼近寄存器模数转换器 (ADC)。对于低偏斜多相位时钟，建议使用具有减少偏移的延迟锁定环 (DLL) 相位检测器 (PD) 来生成时钟之间的偏斜。通过多路复用来自 DLL 的主时钟，可以补偿由大型 TI-ADC 中大面积分布式子 ADC 引起的不同时钟路径延迟。子通道中的偏移和偏斜通过额外的专用子通道在后台在芯片上校准。原型芯片采用 40 纳米 CMOS 工艺实现，有效面积为 0.36 平方毫米。转换速率为 32 GS/s 时，原型 ADC 的实测 SFDR 和 SNDR 分别为 43.1 和 31.4 dB。ADC，包括输入缓冲器，