In this brief, analytical expressions for the metastability voltage of latch-type comparators at sub-threshold operation are advanced. Drain induced barrier lowering (DIBL) and body bias effects are investigated in order to achieve an appropriate model for fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Since, metastability voltage variations have been widely studied as the major cause of latch input offset, statistical expressions are also derived to estimate the yield of latch-type comparators. The analytical results show close agreement with extensive HSPICE simulations using a 28-nm ultra-thin body and buried oxide (UTBB) FD-SOI CMOS technology.

中文翻译：

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28 nm UTBB FD-SOI CMOS 技术中亚稳态电压的闭式分析

在这个简介中，提出了锁存型比较器在亚阈值操作时的亚稳态电压的解析表达式。研究了漏极诱导势垒降低 (DIBL) 和体偏置效应，以便为完全耗尽的绝缘体上硅 (FD-SOI) CMOS 技术实现合适的模型。由于亚稳态电压变化已被广泛研究为锁存输入偏移的主要原因，因此还推导出统计表达式来估计锁存型比较器的良率。分析结果显示与使用 28 纳米超薄体和埋氧 (UTBB) FD-SOI CMOS 技术的广泛 HSPICE 模拟非常吻合。