This brief presents a 12-bit 2-way time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). This brief applied the master clock sampling and gain/offset correction schemes to mitigate channel mismatch errors. In the channel ADC, the subrange SAR ADC architecture was used to maintain high-speed and low-power features. A common bootstrapping circuit was proposed for suppressing the sampling error between coarse and fine ADCs. An intrinsic random sequence was applied to the capacitor swapping. The prototype ADC was fabricated using 65-nm CMOS technology, and it consumed 3 mW from a 1.2-V supply at a sampling rate of 160-MS/s. The measured peak signal-to-noise ratio and spurious-free dynamic range were 60.5 and 80 dB, respectively. The measured peak effective number of bits was 9.76, which is equivalent to a figure-of-merit of 21.6 fJ/conversion-step.

中文翻译：

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65nm CMOS 中的 3mW 12b 160MS/s 2 路时间交错子范围 SAR ADC

本简介介绍了 12 位 2 路时间交错 (TI) 逐次逼近寄存器 (SAR) 模数转换器 (ADC)。本简介应用主时钟采样和增益/偏移校正方案来减轻通道失配错误。在通道 ADC 中，子范围 SAR ADC 架构用于保持高速和低功耗特性。提出了一种通用自举电路来抑制粗略和精细 ADC 之间的采样误差。对电容器交换应用了固有随机序列。原型 ADC 是使用 65-nm CMOS 技术制造的，它在 160-MS/s 的采样率下从 1.2-V 电源消耗 3 mW。测得的峰值信噪比和无杂散动态范围分别为 60.5 和 80 dB。测得的峰值有效位数为 9.76，