In this brief, a dual-supply two-stage op-amp is proposed for a 12-b 1 GS/s pipeline ADC, which is composed of a low-voltage supply pre-amplifier and a high-voltage supply amplifier. Its closed-loop bandwidth reaches to 5.2 GHz, and the phase margin is larger than 60°. The closed-loop amplifier can settle to 99.95% accuracy within 230 ps, which satisfies the harsh requirements of the first-stage MDAC. The proposed op-amp was employed in a single-channel 12-b 1 GS/s pipeline ADC. The ADC is powered by 1.3 V and the op-amp is powered by dual-supply voltage of 1.3 V and 2.5 V. The ADC fabricated in 65 nm CMOS process consumes 360 mW at 1 GS/s. It achieves an SNDR of 61.9 dB and an SFDR of 72.6 dB with 30 MHz input signal, while maintaining an SNDR > 56.0 dB and SFDR > 69.0 dB in the entire 500 MHz Nyquist band.

中文翻译：

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一种用于高速流水线 ADC 应用的双电源两级 CMOS 运算放大器

在本简报中，提出了用于 12-b 1 GS/s 流水线 ADC 的双电源两级运算放大器，它由低压电源前置放大器和高压电源放大器组成。其闭环带宽达到5.2GHz，相位裕度大于60°。闭环放大器可以在 230 ps 内建立到 99.95% 的精度，满足第一级 MDAC 的苛刻要求。建议的运算放大器用于单通道 12-b 1 GS/s 流水线 ADC。ADC 由 1.3 V 供电，运算放大器由 1.3 V 和 2.5 V 双电源供电。采用 65 nm CMOS 工艺制造的 ADC 在 1 GS/s 时消耗 360 mW。它在 30 MHz 输入信号下实现了 61.9 dB 的 SNDR 和 72.6 dB 的 SFDR，同时在整个 500 MHz 奈奎斯特频带中保持了 SNDR > 56.0 dB 和 SFDR > 69.0 dB。