This brief introduces a hardware complexity reduction method for successive cancellation list (SCL) decoders. Specifically, we propose to use a sorting scheme so that $L$ paths with smallest path metrics are also sorted according to their path indexes for path pruning. We prove that such sorting scheme reduces the input number of multiplexers in any hardware implementation of SCL decoding from $L$ to $(L/2+1)$ without any changes in the decoding latency. Field programmable gate array (FPGA) implementations show that the proposed method achieves significant gain in hardware consumptions, especially for large list sizes and block lengths.

中文翻译：

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一种连续取消列表解码的复杂度降低方法

本简介介绍了一种用于连续消除列表 (SCL) 解码器的硬件复杂度降低方法。具体来说，我们建议使用排序方案，以便 $L$ 具有最小路径度量的路径也根据它们的路径索引进行排序以进行路径修剪。我们证明这种排序方案减少了 SCL 解码的任何硬件实现中多路复用器的输入数量 $L$ 至 $(L/2+1)$ 解码延迟没有任何变化。现场可编程门阵列 (FPGA) 实现表明，所提出的方法在硬件消耗方面取得了显着收益，特别是对于大列表大小和块长度。