In general, existing logic synthesis methods for majority logic are limited to 3-input gates (maj-3). However, since majority gates with larger fan-in have been proposed for different emerging nanotechnologies, it has become important to consider such gates in the synthesis process. This paper proposes a novel majority logic synthesis flow where the gates can have an arbitrary number of inputs. The proposed approach is based on the relationship between majority and threshold logic functions. The proposed methods obtain an average reduction of 10% on the number of nodes when compared to a previous work that uses both maj-3 and maj-5 gates. When compared to the previous maj-3 synthesis, the average reduction on number of nodes is 14%.

中文翻译：

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新兴技术的主要逻辑综合

通常，多数逻辑的现有逻辑综合方法仅限于 3 输入门 (maj-3)。然而，由于已经为不同的新兴纳米技术提出了具有更大扇入的多数门，因此在合成过程中考虑此类门变得很重要。本文提出了一种新颖的多数逻辑综合流程，其中门可以具有任意数量的输入。所提出的方法基于多数和阈值逻辑函数之间的关系。与使用 maj-3 和 maj-5 门的先前工作相比，所提出的方法平均减少了 10% 的节点数量。与之前的 maj-3 综合相比，节点数量平均减少了 14%。