Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due to their sheer complexity, insufficient to transport designs through modern circuit design flows. Instead, each design automation tool lowers HDLs to its own Intermediate Representation (IR). These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow. To solve this problem, we propose the LLHD multi-level IR. LLHD is designed as simple, unambiguous reference description of a digital circuit, yet fully captures existing HDLs. We show this with our reference compiler on designs as complex as full CPU cores. LLHD comes with lowering passes to a hardware-near structural IR, which readily integrates with existing tools. LLHD establishes the basis for innovation in HDLs and tools without redundant compilers or disjoint IRs. For instance, we implement an LLHD simulator that runs up to 2.4x faster than commercial simulators but produces equivalent, cycle-accurate results. An initial vertically-integrated research prototype is capable of representing all levels of the IR, implements lowering from the behavioural to the structural IR, and covers a sufficient subset of SystemVerilog to support a full CPU design.

中文翻译：

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LLHD：硬件描述语言的多级中间表示

现代硬件描述语言 (HDL)，例如 SystemVerilog 或 VHDL，由于其过于复杂，不足以通过现代电路设计流程传输设计。相反，每个设计自动化工具都将 HDL 降低到其自己的中间表示 (IR)。这些工具是单片的并且大多是专有的，在它们的 HDL 实现方面存在分歧，虽然存在许多冗余 IR，但今天没有 IR 可以在整个电路设计流程中使用。为了解决这个问题，我们提出了 LLHD 多级 IR。LLHD 被设计为数字电路的简单、明确的参考描述，但完全捕获现有的 HDL。我们用我们的参考编译器在像完整 CPU 内核一样复杂的设计中展示了这一点。LLHD 带有降低到接近硬件的结构 IR 的通道，它很容易与现有工具集成。LLHD 为 HDL 和工具的创新奠定了基础，无需冗余编译器或不相交的 IR。例如，我们实施了一个 LLHD 模拟器，其运行速度比商业模拟器快 2.4 倍，但产生等效的、周期准确的结果。最初的垂直整合研究原型能够代表所有层次的 IR，实现从行为到结构 IR 的降低，并涵盖足够的 SystemVerilog 子集以支持完整的 CPU 设计。