A novel trombone topology has been introduced for achieving controllable true time delay. The prominent aspect of the proposed topology is the ability to provide discrete variable delay with minimum insertion loss variation with delay settings. Furthermore, the effects of source impedance, output load, and line-terminating loads’ impedance mismatch on group delay variation are theoretically investigated for the proposed trombone topology. Moreover, based on this new topology, a prototype trombone delay circuit has been designed and fabricated in 0.18- $\mu \text{m}$ CMOS technology, operating over the frequency bandwidth of 8–18 GHz. This 3-bit delay integrated circuit provides a maximum delay of 109.3 ps with 15.6-ps delay step and utilizes conventional passive second-order all-pass network (APN) and novel passive fourth-order APN delay cells. Measurement results indicate an average insertion loss of 18.2–22.5 dB over the intended frequency band with a relatively low loss variation of less than ±1 dB for all delay settings. Measured group delay rms error is less than 4 ps. The core of the fabricated circuit occupies an area of $0.9\times2.1$ mm² and draws 13.4 mA from a 3.3-V supply.

中文翻译：

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用于宽带真延时实现的新型长号拓扑

引入了一种新颖的长号拓扑来实现可控的真实时间延迟。所提出的拓扑结构的突出方面是能够提供离散可变延迟，并且随着延迟设置的插入损耗变化最小。此外，对于所提出的长号拓扑，从理论上研究了源阻抗、输出负载和线路端接负载阻抗失配对群延迟变化的影响。此外，基于这种新的拓扑结构，原型长号延迟电路已经设计和制造在 0.18- $\mu \text{m}$ CMOS 技术，在 8–18 GHz 的频率带宽上运行。这种 3 位延迟集成电路提供 109.3 ps 的最大延迟和 15.6 ps 延迟步长，并利用传统的无源二阶全通网络 (APN) 和新型无源四阶 APN 延迟单元。测量结果表明，对于所有延迟设置，预期频带内的平均插入损耗为 18.2–22.5 dB，且损耗变化相对较低，小于 ±1 dB。测得的群延迟均方根误差小于 4 ps。制作电路的核心占用面积为 $0.9\times2.1$ mm ²并从 3.3V 电源汲取 13.4mA 电流。