This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on $0.18~\mu \text{m}$ CMOS technology with an operational range of 350~900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 mm2.

中文翻译：

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一种用于测距传感器TDC的6.8mW全数字延迟锁定环的数字控制抖动消除设计

本文介绍了一种 6.8 mW 全数字延迟锁定环 (ADDLL) 的设计，具有数控抖动消除 (DCDC)，用于测距传感器中的时间数字转换器 (TDC)。ADDLL 在锁相期间使用累加器 (ACC) 来控制数控延迟线 (DCDL) 的延迟，与模拟延迟锁定环 (DLL) 相比，它使用更少的功率和面积。在锁定状态下，ACC 值由于闭环操作而抖动。提出了一种数字控制器来检测锁定状态、执行抖动消除并选择最佳 ACC 值以控制 TDC 操作的副本 DCDL 的延迟。它有助于减少 ADDLL 中的抖动。此外，它还具有在嘈杂环境中防止故障、错误锁定和解锁的鲁棒性。625 MHz 下的 ADDLL 峰峰值抖动和 RMS 抖动为 6。分别为 5 ps 和 1.2 ps。ADDLL 包括 DCDC 是在 $0.18~\mu\text{m}$ CMOS 技术上实现的，操作范围为 350~900 MHz。它在 625 MHz 功率和 1.8 V 电源下仅消耗 6.8 mW。面积利用率为0.06 mm2。