This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering ( $\vert \text{S}\vert$ ) parameters of the resonators. In return, sharp $\vert \text{S}\vert $ -parameters slope enhances the resonator loaded quality (Q) factor without compromising the unloaded Q-factor. In addition, the transmission pole can be realized near the second harmonic of the oscillation. This allocation of the transmission pole leads to the cancellation of this second harmonic and a further reduction of the phase noise. The proposed theory is verified by three different designs based on defected ground structure (DGS) resonators. These designs realized a low-band transmission pole before the parallel resonance, a high-band transmission pole after the parallel resonance, and dual-band transmission poles around the parallel resonance. First, each design is verified and compared to the others using circuit and electromagnetic simulations to establish the Q-factor improvement. Then, each of the resonators is utilized in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in 0.18- $\mu $ m CMOS technology and measured. The measurement results are in good agreement with the simulations, which confirm our claim about the proposed theory.

中文翻译：

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在 0.18 微米 CMOS 技术中使用多谐振缺陷接地结构谐振器降低 K 波段 VCO 的相位噪声

这项工作提出了一种新理论，通过在 LC 谐振回路的并联谐振周围引入一个或多个传输极，来降低互补金属氧化物半导体 (CMOS) 工艺中 K 波段压控振荡器 (VCO) 的相位噪声。除了 LC 谐振回路的并联谐振外，还引入了传输极点，从而锐化了散射的裙边特性（ $\vert \text{S}\vert$ ) 谐振器的参数。作为回报，锋利的 $\vert \text{S}\vert $ -参数斜率提高了谐振器加载质量 (Q) 因子，而不会影响卸载 Q 因子。此外，可以在振荡的二次谐波附近实现传输极点。传输极点的这种分配导致消除该二次谐波并进一步降低相位噪声。所提出的理论通过基于缺陷接地结构 (DGS) 谐振器的三种不同设计得到验证。这些设计实现了并联谐振前的低频段传输极点、并联谐振后的高频段传输极点和并联谐振周围的双频段传输极点。首先，每个设计都经过验证，并使用电路和电磁仿真与其他设计进行比较，以确定 Q 因子的改进。然后，每个谐振器都用于差分 VCO 拓扑结构，并且确认了布局后仿真中的相位噪声降低。最后，在 0.18- $\亩 $ m CMOS 技术和实测。测量结果与模拟非常吻合，这证实了我们对所提出理论的主张。