A continuous-time (CT) second-order $\Delta \Sigma $ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator which results in significant power and noise reduction compared to previous prototype. Excess loop delay in the proposed CDC is countered through judicious selection of loop parameters and no auxiliary DAC is used for loop delay compensation. A prototype CDC is implemented in 65nm CMOS and achieves 76dB dynamic range at a bandwidth of 0.2MHz from 1V supply with a walden FoM of 48fJ/step which is $9\times $ improvement on the state-of-the-art.

中文翻译：

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基于 76dB DR、48 fJ/Step 二阶 VCO 的电流数字转换器

连续时间 (CT) 二阶 $\Delta \Sigma $ 本文介绍了电流数字转换器 (CDC)。所提出的 CDC 使用两个电流控制环形振荡器作为相域积分器来实现二阶量化噪声整形。所提议的 CDC 使用电流重用架构，其中反馈数模转换器 (DAC) 用于偏置第一个积分器，与之前的原型相比，这可显着降低功耗和噪声。所提议的 CDC 中的过多环路延迟是通过明智地选择环路参数来抵消的，并且没有使用辅助 DAC 来进行环路延迟补偿。原型 CDC 在 65nm CMOS 中实现，在 0.2MHz 带宽下从 1V 电源实现 76dB 动态范围，瓦尔登 FoM 为 48fJ/step，即 $9\times $ 对最先进技术的改进。