The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic refresh cycles, which are determined according to the worst-case data retention time (DRT) across process, voltage and temperature (PVT) variations. Even though several DRT characterization methodologies have been reported in literature, they often require unfeasible run-times for accurate DRT evaluation, or they result in highly pessimistic design margins due to their inaccuracy. In this work, we propose an current-based DRT (IDRT) characterization methodology that enables accurate DRT evaluation across process variations without the need for a large number of costly electronic design automation (EDA) software licenses. The presented approach is compared with other DRT characterization methodologies for both accuracy and run-time across several gain-cell structures at different process technologies, providing less than a 4% DRT error and over $100\times $ shorter run-time compared to a conventional DRT evaluation methodology.

中文翻译：

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整个设计和变化空间中增益单元嵌入式 DRAM 的基于电流的数据保留时间特性

数据密集型应用的兴起导致对高密度和低功耗片上嵌入式存储器的需求不断增加。增益单元嵌入式 DRAM (GC-eDRAM) 是传统静态随机存取存储器 (SRAM) 的逻辑兼容替代品，可提供更高的密度、更低的泄漏功率和双端口操作。然而，为了保持存储的数据，GC-eDRAM 需要定期刷新周期，这是根据跨工艺、电压和温度 (PVT) 变化的最坏情况数据保留时间 (DRT) 确定的。尽管文献中已经报道了几种 DRT 表征方法，但它们通常需要不可行的运行时间来进行准确的 DRT 评估，或者由于它们的不准确性导致高度悲观的设计裕度。在这项工作中，我们提出了一种基于电流的 DRT (IDRT) 表征方法，该方法可以跨过程变化进行准确的 DRT 评估，而无需大量昂贵的电子设计自动化 (EDA) 软件许可证。所提出的方法与其他 DRT 表征方法在不同工艺技术的几种增益单元结构的精度和运行时间方面进行了比较，与传统方法相比，DRT 误差小于 4%，运行时间缩短了 100 多美元。 DRT 评估方法。