This work presents a compact CMOS Image Sensor (CIS) architecture enabling embedded object recognition facilitated by a dedicated end-of-column Compressive Sensing (CS), reducing on-chip memory needs. Our sensing scheme is based on a combination of random modulations and permutations leading to an implementation with very limited hardware impacts. It is designed to meet both theoretical (i.e., stable embedding, measurements incoherence) and practical requirements (i.e., silicon footprint, power consumption). The only additional hardware compared to a standard CIS architecture using first order incremental Sigma-Delta (ΣA) Analog to Digital Converter (ADC) are a pseudo-random data mixing circuit, an in-ΣA ±1 modulator and a small Digital Signal Processor (DSP). On the algorithmic side, three variants are presented to perform the inference on compressed measurements with a tunable complexity (i.e., onevs.-all SVM, hierarchical SVM and small ANN with 1-D maxpooling). An object recognition accuracy of ≃98.8% is reached on the COIL database (COIL, 100 classes) using our dedicated Neural Network classifier. We stress that the signal-independent dimensionality reduction performed by our dedicated CS scheme (1/480 in 480 × 640 VGA resolution case) allows to dramatically reduce memory requirements mainly related to the remotely learned coefficients used for the inference stage.

中文翻译：

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基于随机调制和排列的嵌入式推理的硬件兼容的压缩图像传感器架构


这项工作提出了一种紧凑的 CMOS 图像传感器 (CIS) 架构，可通过专用的柱端压缩传感 (CS) 实现嵌入式物体识别，从而减少片上内存需求。我们的传感方案基于随机调制和排列的组合，从而实现对硬件影响非常有限的实现。它的设计旨在满足理论（即稳定嵌入、测量不相干）和实际要求（即硅足迹、功耗）。与使用一阶增量 Sigma-Delta (ΣA) 模数转换器 (ADC) 的标准 CIS 架构相比，唯一额外的硬件是伪随机数据混合电路、ΣA ±1 调制器和小型数字信号处理器（ DSP）。在算法方面，提出了三种变体来对复杂度可调的压缩测量进行推理（即，onevs.-all SVM、分层 SVM 和具有 1-D maxpooling 的小型 ANN）。使用我们专用的神经网络分类器，COIL 数据库（COIL，100 个类别）的对象识别准确度达到≃98.8%。我们强调，我们的专用 CS 方案（在 480 × 640 VGA 分辨率情况下为 1/480）执行的与信号无关的降维可以显着减少主要与用于推理阶段的远程学习系数相关的内存需求。