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Deep Neural Network Acceleration Based on Low-Rank Approximated Channel Pruning
IEEE Transactions on Circuits and Systems I: Regular Papers ( IF 5.2 ) Pub Date : 2020-04-01 , DOI: 10.1109/tcsi.2019.2958937
Zhen Chen , Zhibo Chen , Jianxin Lin , Sen Liu , Weiping Li

Acceleration and compression on deep Convolutional Neural Networks (CNNs) have become a critical problem to develop intelligence on resource-constrained devices. Previous channel pruning can be easily deployed and accelerated without specialized hardware and software. However, weight-level redundancy is not well explored in channel pruning, which results in a relatively low compression ratio. In this work, we propose a Low-rank Approximated channel Pruning (LAP) framework to tackle this problem with two targeted steps. First, we utilize low-rank approximation to eliminate the redundancy within filter. This step achieves acceleration, especially in shallow layers, and also converts filters into smaller compact ones. Then, we apply channel pruning on the approximated network in a global way and obtain further benefits, especially in deep layers. In addition, we propose a spectral norm based indicator to coordinate these two steps better. Moreover, inspired by the integral idea adopted in video coding, we propose an evaluator based on Integral of Decay Curve (IDC) to judge the efficiency of various acceleration and compression algorithms. Ablation experiments and IDC evaluator prove that LAP can significantly improve channel pruning. To further demonstrate the hardware compatibility, the network produced by LAP obtains impressive speedup efficiency on the FPGA.

中文翻译:

基于低秩近似信道剪枝的深度神经网络加速

深度卷积神经网络 (CNN) 上的加速和压缩已成为在资源受限设备上开发智能的关键问题。无需专门的硬件和软件即可轻松部署和加速先前的通道修剪。然而,在通道修剪中没有很好地探索权重级冗余,这导致压缩率相对较低。在这项工作中,我们提出了一个低秩近似通道剪枝 (LAP) 框架,通过两个有针对性的步骤来解决这个问题。首先,我们利用低秩近似来消除滤波器内的冗余。这一步实现了加速,尤其是在浅层中,并将过滤器转换为更小的紧凑型过滤器。然后,我们以全局方式在近似网络上应用通道修剪并获得进一步的好处,尤其是在深层。此外,我们提出了一个基于频谱范数的指标来更好地协调这两个步骤。此外,受视频编码中采用的积分思想的启发,我们提出了一种基于衰减曲线积分(IDC)的评估器来判断各种加速和压缩算法的效率。消融实验和 IDC 评估器证明 LAP 可以显着改善通道修剪。为了进一步证明硬件兼容性,LAP 制作的网络在 FPGA 上获得了令人印象深刻的加速效率。消融实验和 IDC 评估器证明 LAP 可以显着改善通道修剪。为了进一步证明硬件兼容性,LAP 制作的网络在 FPGA 上获得了令人印象深刻的加速效率。消融实验和 IDC 评估器证明 LAP 可以显着改善通道修剪。为了进一步证明硬件兼容性,LAP 制作的网络在 FPGA 上获得了令人印象深刻的加速效率。
更新日期:2020-04-01
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