This paper presents a fully-integrated integer- $N$ frequency synthesizer that uses switched-gain control (SGC) within the phased-locked loop (PLL). Unlike other methods to improve PLL performance, the SGC method exploits the potential advantages of positive feedback within the main loop. The proposed SGC-PLL uses a supervisor with four switching regions in the phase plane to minimize the effects of circuit non-linearity within the PLL. This results in significantly lower settling time than conventional designs while maintaining similar phase noise. The design has been implemented in the UMC 180 nm CMOS process for an output frequency range of 1-16 MHz. Test results show that the proposed approach decreases the settling time by a maximum of 24.7% compared to a conventional PLL with the same loop parameters.

中文翻译：

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使用开关增益控制的快速稳定整数 N 频率合成器

本文介绍了一种完全集成的整数-$N$ 频率合成器，它在锁相环 (PLL) 内使用开关增益控制 (SGC)。与提高 PLL 性能的其他方法不同，SGC 方法利用了主循环内正反馈的潜在优势。建议的 SGC-PLL 在相平面中使用具有四个开关区域的监控器，以最大限度地减少 PLL 内电路非线性的影响。与传统设计相比，这导致稳定时间显着缩短，同时保持相似的相位噪声。该设计已在 UMC 180 nm CMOS 工艺中实现，输出频率范围为 1-16 MHz。测试结果表明，与具有相同环路参数的传统 PLL 相比，所提出的方法最多可减少 24.7% 的建立时间。