This paper investigates the suitability of full duplex simultaneous bidirectional (FD-SBD) signaling as a method to theoretically double the aggregate data transfer per pin for ultra-short-reach links. Advantages as well as challenges associated with differential FD-SBD links are described, and comparisons are made with single-ended and multilevel signaling schemes. FD-SBD links require a hybrid to recover the weak received signal from the large self-interfering transmitted signal. After providing a summary of prior-art high-speed hybrids, which often utilize replica drivers and current-mode signaling, two voltage-mode hybrids are presented and compared to enable low-power FD-SBD links at high data rates without using any replica drivers. This includes an R- $G_{m}$ driver, as well as a resistor-bridge driver derived from a Wheatstone-bridge. It is shown that maintaining a uniform termination impedance is important to support FD-SBD signaling on low insertion-loss links. Accordingly, a resistor-bridge hybrid utilizing an averaging resistor embedded in the output transimpedance amplifier based voltage-mode driver is implemented. A prototype implemented in a 65 nm CMOS process is measured within a transceiver front-end at an aggregate data rate of 15 Gb/s over a short differential channel with 2.5 dB insertion loss at 3.75 GHz on a 4-layer FR4 PCB. The energy/bit for the transceiver front-end is 1.35 pJ/b at an aggregate data rate of 15 Gb/s.

中文翻译：

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全双工同时双向信令链路的低功耗混合电路设计

本文研究了全双工同时双向 (FD-SBD) 信号作为一种方法的适用性，该方法理论上可将超短距离链路的每个引脚的聚合数据传输加倍。描述了与差分 FD-SBD 链路相关的优点和挑战，并与单端和多级信令方案进行了比较。FD-SBD 链路需要混合器来从大的自干扰传输信号中恢复微弱的接收信号。在提供了通常使用副本驱动器和电流模式信号的现有技术高速混合的总结之后，提出并比较了两种电压模式混合，以在不使用任何副本的情况下以高数据速率启用低功率 FD-SBD 链路司机。这包括一个 R- $G_{m}$ 驱动器，以及一个源自惠斯通电桥的电阻桥驱动器。结果表明，保持统一的终端阻抗对于支持低插入损耗链路上的 FD-SBD 信号非常重要。因此，实现了利用嵌入在基于输出跨阻放大器的电压模式驱动器中的平均电阻器的电阻器桥混合器。在 65 纳米 CMOS 工艺中实现的原型在收发器前端内以 15 Gb/s 的聚合数据速率通过短差分通道进行测量，在 3.75 GHz 的 4 层 FR4 PCB 上插入损耗为 2.5 dB。收发器前端的能量/比特为 1.35 pJ/b，聚合数据速率为 15 Gb/s。利用嵌入在输出跨阻放大器中的平均电阻器实现了一个电阻桥混合器，该输出跨阻放大器基于电压模式驱动器。在 65 纳米 CMOS 工艺中实现的原型在收发器前端内以 15 Gb/s 的聚合数据速率通过短差分通道进行测量，在 3.75 GHz 的 4 层 FR4 PCB 上插入损耗为 2.5 dB。收发器前端的能量/比特为 1.35 pJ/b，聚合数据速率为 15 Gb/s。利用嵌入在输出跨阻放大器中的平均电阻器实现了一个电阻桥混合器，该输出跨阻放大器基于电压模式驱动器。在 65 纳米 CMOS 工艺中实现的原型在收发器前端内以 15 Gb/s 的聚合数据速率通过短差分通道进行测量，在 3.75 GHz 的 4 层 FR4 PCB 上插入损耗为 2.5 dB。收发器前端的能量/比特为 1.35 pJ/b，聚合数据速率为 15 Gb/s。