Abstract

A simple energy-efficient switching procedure is proposed to reduce the total number of switches and facilitate the capacitors matching requirements in SAR ADCs. The main idea is that the coupling capacitor (C_C) is utilized as the same as the unit one, which is applied for LSB charge production. After the reset phase, only the MSB capacitor is connected to the input potential, while the other experience either low and high reference potential; hence, a simplified switching strategy with 55% reduction in number of switches is retrieved. Post-layout simulation results confirm SNDR and ENOB of around 80 dB and 13 bit, respectively, at Nyquist input frequency when the conversion rate is 17 MS/s. In these conditions, FOMW and FOMS reach to 139.9 fJ/Conv-Step and 166.15 dB, respectively. Also, INL and DNL would experience the maximum level of + 0.95/− 0.58 LSB and + 0.63/− 0.74 LSB, respectively. The proposed ADC occupies active area of 1.7 mm² and consumes around 20.6 mW power at 5 V supply and 17 MS/s conversion rate. Post-layout simulation results are performed using the HSPICE BSIM3 model of a 0.50 µm CMOS process.

中文翻译：

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具有节能开关策略的17 MS / s SAR ADC

摘要

提出了一种简单的节能开关过程，以减少开关的总数并促进SAR ADC中电容器匹配的要求。主要思想是耦合电容器（C _C）与用于LSB电荷生产的单元一相同。复位阶段之后，仅将MSB电容器连接到输入电势，而另一个则经历低和高参考电势。因此，获得了简化的开关策略，将开关数量减少了55％。布局后的仿真结果证实，当转换速率为17 MS / s时，在奈奎斯特输入频率下，SNDR和ENOB分别约为80 dB和13位。在这些条件下，FOMW和FOMS分别达到139.9 fJ / Conv-Step和166.15 dB。同样，INL和DNL的最大级别分别为+ 0.95 /-0.58 LSB和+ 0.63 /-0.74 LSB。拟议的ADC占用1.7 mm ^2的有效面积在5 V电源和17 MS / s转换速率下消耗约20.6 mW功率。使用HSPICE BSIM3模型（0.50 µm CMOS工艺）执行布局后仿真结果。