In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl₂-based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.

中文翻译：

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直径低至 20 nm 的垂直 Ge Gate-All-Around 纳米线 pMOSFET

在这项工作中，我们展示了采用 CMOS 兼容自上而下方法制造的垂直 Ge 全环栅 (GAA) 纳米线 pMOSFET。通过优化的基于Cl ₂的干法蚀刻和自限性数字蚀刻，获得了直径低至 20 nm 且纵横比为~11 的垂直 Ge 纳米线。采用 GAA 架构、氧化后钝化和 NiGe 触点，高性能 Ge 纳米线 pMOSFET 表现出 66 mV/dec 的低 SS、35 mV/V 的小 DIBL 和高 $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ 比率 ${2.1}\times {10}^{{6}}$ . 还通过与温度相关的测量来研究电行为。实验 SS 与理想 kT/q 之间的偏差 $\cdot $ ln10 值源于界面陷阱的密度 $(\text {D}_{\text {it}})$ . 我们的测量表明，降低顶部接触电阻是进一步提高垂直 Ge GAA 纳米线晶体管性能的关键。