In this letter, an improved measurement method for power transistors is proposed to obtain drain-current characteristics as a function of drain-source voltage ( ${I}_{\text {d}}$ – ${V}_{\text {ds}}$ ) in high-voltage and high-current (HVHC) ranges. A simple double pulse test (DPT) is utilized in our previous method. However, the self-heating of the device under test (DUT) is not ignorable in the range of high ${I}_{\text {d}}$ . The improved test circuit is equipped with an additional transistor connected in parallel to DUT in order to prevent the flow of a large current into DUT before the measurement. When a trench-gate type SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) is used as a DUT, the power loss of the DUT decreases by about 80%. The transient thermal analysis shows that the die temperature rise is suppressed by up to 10 °C in about 200 A ranges. The newly obtained ${I}_{\text {d}}$ – ${V}_{\text {ds}}$ characteristics are utilized to model the SiC trench MOSFET. The device model reproduces the measured switching waveforms very accurately.

中文翻译：

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降低自热改善功率晶体管的高压大电流Id-Vds测量方法

在这封信中，提出了一种改进的功率晶体管测量方法，以获得作为漏源电压函数的漏电流特性（ ${I}_{\text {d}}$ —— ${V}_{\text {ds}}$ ) 在高电压和高电流 (HVHC) 范围内。我们之前的方法使用了简单的双脉冲测试 (DPT)。然而，被测器件 (DUT) 的自热在高范围内是不可忽视的。 ${I}_{\text {d}}$ . 改进后的测试电路配备了一个与 DUT 并联的附加晶体管，以防止大电流在测量前流入 DUT。当使用沟槽栅型 SiC MOSFET（金属氧化物半导体场效应晶体管）作为 DUT 时，DUT 的功率损耗降低了约 80%。瞬态热分析表明，在大约 200 A 的范围内，芯片温升最多被抑制 10 °C。新获得的 ${I}_{\text {d}}$ —— ${V}_{\text {ds}}$ 特性被用来模拟 SiC 沟槽 MOSFET。器件模型非常准确地再现了测得的开关波形。