Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( $L_{\textbf {G}}$ ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to $L_{\textbf {G}}$ of 16 nm offering a larger on-current ( $I_{\textbf {ON}}$ ) and slightly better sub-threshold characteristics. Below $\text{L}_{\textbf {G}}$ of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( $I_{\textbf {OFF}}$ ), and the largest $I_{\textbf {ON}}/I_{\textbf {OFF}}$ ratio out of the three architectures. However, the NW FET suffers from early $I_{\textrm {ON}}$ saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

中文翻译：

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面向未来技术节点的 FinFET、纳米片和纳米线 FET 架构的基准测试

纳米片 (NS) 和纳米线 (NW) FET 架构缩放到栅极长度 ( $L_{\textbf {G}}$ ) 的 16 nm 及以下以等效的 FinFET 为基准。使用具有基于量子校正的集成 2D Schrödinger 方程的 3D 有限元漂移扩散/蒙特卡罗模拟工具箱来预测器件性能。NS FET 是高性能 (HP) 应用中 FinFET 的可行替代品，当按比例缩小到 $L_{\textbf {G}}$ 16 nm 提供更大的导通电流（ $I_{\textbf {ON}}$ ) 和稍微好一点的亚阈值特性。以下 $\text{L}_{\textbf {G}}$ 16 nm 时，NW FET 成为最有前途的架构，可提供几乎理想的亚阈值摆幅、最小的关断电流（ $I_{\textbf {OFF}}$ )，以及最大的 $I_{\textbf {ON}}/I_{\textbf {OFF}}$ 三种架构的比例。然而，NW FET 受制于早期 $I_{\textrm {ON}}$ 可以通过最小化界面粗糙度和/或优化器件主体中的掺杂分布来解决增加的栅极偏置饱和。