A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration settling time, independent of the dynamic range of the load or output capacitor value. Measurement results of a 10-bit PG design demonstrate a droop of 100 mV for 500 mA (2 A/ns $di/dt$ ) with settling times < 20 ns. The CDLDO design is presented with the key equations and timing diagrams to show the operating principle of the concept. Methods to accommodate resiliency to process, voltage and temperature (PVT) and wide dynamic voltage frequency scaling (DVFS) conditions are also discussed in detail.

中文翻译：

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具有快速瞬态响应的 22-nm CMOS 中的变化自适应集成计算数字 LDO

提出了一种具有事件驱动计算控制器 (CC) 的变化自适应计算数字低压差 (CDLDO) 调节器，它计算所需的功率门 (PG) 数量，这与传统的基于 IIR 滤波器的控制技术不同，以调节输出电压对于任何负载/参考瞬态。CC 确保~ns 瞬态响应具有确定性的两事件持续时间稳定时间，与负载或输出电容器值的动态范围无关。10 位 PG 设计的测量结果表明，500 mA (2 A/ns $di/dt$) 的下降为 100 mV，稳定时间 < 20 ns。CDLDO 设计提供了关键方程和时序图，以展示该概念的工作原理。适应处理弹性的方法，