Network-on-Chip (NoC) paradigm has been proposed as an auspicious solution to handle the strict communication requirements between the increasingly large number of cores on a single multi and many-core chips. However, NoC systems are exposed to a variety of manufacturing, design and energetic particles factors making them vulnerable to permanent (hard) faults and transient (soft) errors. In this paper, we present a comprehensive soft error and hard fault tolerant 3D-NoC architecture, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of adaptive algorithms, 3D-FETO is capable of detecting and recovering from soft errors occurring in the routing pipeline stages and is leveraging on reconfigurable components to handle permanent faults occurrence in links, input buffers, and crossbar. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors while ensuring graceful performance degradation, minimizing the additional hardware complexity and remaining power-efficient.

中文翻译：

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用于可靠 3D-NoC 系统的软错误和硬错误容忍架构和路由算法

片上网络 (NoC) 范式已被提议作为一种吉祥的解决方案，以处理单个多核和众核芯片上越来越多的核之间的严格通信要求。然而，NoC 系统受到各种制造、设计和高能粒子因素的影响，使它们容易受到永久性（硬）故障和瞬态（软）错误的影响。在本文中，我们提出了一种全面的软错误和硬容错 3D-NoC 架构，名为 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO)。借助自适应算法，3D-FETO 能够检测路由管道阶段发生的软错误并从中恢复，并利用可重新配置的组件来处理链路、输入缓冲区和交叉开关中发生的永久性故障。