The evolvable hardware literature reports several methods for the evolution of digital circuits. However, there is a large variability in the set of problems and the appropriate metrics used for the evaluation of the results. In this paper, we propose a set of representative problems to comparatively evaluate metaheuristics when designing Combinational Logic Circuits (CLCs). We also define a set of performance measurements and descriptive statistics to analyze the results found by the search techniques. As a case study, we compare Cartesian Genetic Programming variants applied to this domain. The results highlight the benefits of the proposed heterogeneous benchmark suite in the analysis of metaheuristics when designing CLCs.

不断发展的硬件文献报道了几种用于数字电路发展的方法。但是，问题集和用于评估结果的适当度量标准存在很大的差异。在本文中，我们提出了一组代表性问题，以便在设计组合逻辑电路（CLC）时比较评估元启发式算法。我们还定义了一组性能指标和描述性统计数据，以分析通过搜索技术找到的结果。作为案例研究，我们比较了应用于该领域的笛卡尔遗传编程变体。结果表明，在设计CLC时，建议的异构基准套件在元启发式分析中的优势。