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Peak-Power-Aware Energy Management for Periodic Real-Time Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( IF 2.9 ) Pub Date : 2020-04-01 , DOI: 10.1109/tcad.2019.2901244
Mohsen Ansari , Amir Yeganeh-Khaksar , Sepideh Safari , Alireza Ejlali

Two main objectives in designing real-time embedded systems are high reliability and low power consumption. Hardware replication (e.g., standby-sparing) can provide high reliability while keeping the power consumption under control. In this paper, we consider a standby-sparing system where the main tasks on primary cores are scheduled by our proposed peak-power-aware earliest-deadline-first policy while the backup tasks on spare cores are scheduled by our proposed peak-power-aware earliest-deadline-late policy to meet the chip thermal design power (TDP) constraint. These policies provide the best opportunity to shift the task executions as much as possible to minimize execution overlaps between main and backup tasks that consume high power consumption. Since TDP is the maximum amount of power generated by a chip that the cooling component is designed to dissipate under any workload, the total power consumption should not be higher than the TDP constraint. When a task finishes successfully a larger portion of its corresponding copy task can be canceled, resulting in a significant amount of peak/average power reduction. To achieve further peak/average power reduction, we use dynamic voltage and frequency scaling and dynamic power management (DPM). The main reason of using DPM is that, once the first copy of each task has finished successfully, its corresponding copy task is terminated, and if there is no more task for execution, the core goes to a low-power mode. We evaluated our scheme under various system configurations. Experiments show that our scheme provides up to 47.6% (on average by 28.2%) peak power reduction compared to four state-of-the-art techniques.

中文翻译:

用于周期性实时应用的峰值功率感知能源管理

设计实时嵌入式系统的两个主要目标是高可靠性和低功耗。硬件复制(例如,备用备用)可以提供高可靠性,同时控制功耗。在本文中,我们考虑了一个备用备用系统,其中主核上的主要任务由我们提出的峰值功率感知最早截止日期优先策略调度,而备用核上的备份任务由我们提出的峰值功率调度-了解最早截止日期延迟策略,以满足芯片热设计功耗 (TDP) 约束。这些策略提供了尽可能多地转移任务执行的最佳机会,以最小化消耗高功耗的主任务和备份任务之间的执行重叠。由于 TDP 是冷却组件设计为在任何工作负载下耗散的芯片产生的最大功率量,因此总功耗不应高于 TDP 约束。当任务成功完成时,可以取消其相应复制任务的较大部分,从而导致峰值/平均功率显着降低。为了进一步降低峰值/平均功率,我们使用动态电压和频率缩放以及动态电源管理 (DPM)。使用DPM的主要原因是,一旦每个任务的第一个副本成功完成,其对应的副本任务就会终止,如果没有更多的任务要执行,内核就会进入低功耗模式。我们在各种系统配置下评估了我们的方案。实验表明,我们的方案提供高达 47.6%(平均 28.
更新日期:2020-04-01
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