Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computing-intensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this paper, a spintronics-based stochastic computing (SC) approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build a stochastic bitstream generator (SBG) for SC with hybrid CMOS/magnetic tunnel junction (MTJ) circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and SC logic. A device-to-architecture level framework is proposed to evaluate the performance of spintronics-based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about $12 {\times }$ than MTJ-based approach with 45% design area overhead and about $26 {\times }$ than FPGA-based approach.

中文翻译：

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SPINBIS：具有随机计算的基于自旋电子学的贝叶斯推理系统

贝叶斯推理是解决统计学习问题的有效方法，尤其是具有不确定性和不完整性的问题。然而，贝叶斯推理是一项计算密集型任务，其效率受到传统计算平台瓶颈的物理限制。在本文中，提出了一种基于自旋电子学的随机计算 (SC) 方法，用于有效的贝叶斯推理。自旋电子器件固有的随机开关行为被用来构建一个随机比特流发生器 (SBG)，用于具有混合 CMOS/磁性隧道结 (MTJ) 电路设计的 SC。为了提高推理效率，利用 SBG 共享策略通过在 SBG 阵列和 SC 逻辑之间集成交换网络来减少所需的 SBG 阵列规模。提出了一种设备到架构级别的框架来评估基于自旋电子学的贝叶斯推理系统 (SPINBIS) 的性能。数据融合应用的实验结果表明，SPINBIS 可以提高约 $12 {\times }$ 比基于 MTJ 的方法具有 45% 的设计面积开销和大约 $26 {\times }$ 而不是基于 FPGA 的方法。