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A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs with Thermal Consideration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( IF 2.9 ) Pub Date : 2020-04-01 , DOI: 10.1109/tcad.2019.2897707
Bi Wu , Pengcheng Dai , Yuanqing Cheng , Ying Wang , Jianlei Yang , Zhaohao Wang , Dijun Liu , Weisheng Zhao

As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip cache capacity increases to sustain the performance scaling. As a result, the cache power occupies a large portion of the total power budget. Spin transfer torque magnetic memory (STT-MRAM) is proposed as a promising solution for the low power cache design due to its high integration density and ultralow leakage power. Nevertheless, the high write power and latency of STT-MRAM become new barriers for the commercialization of this emerging technology. In this paper, we investigate the thermal effect on the access performance of STT-MRAM, and observe that the temperature can affect the write delay and energy significantly. Then, we explore the nonuniform cache access (NUCA) design of the chip-multiprocessors with STT-MRAM-based last level cache (LLC). A thermal aware data migration policy, called “Thermosiphon,” which takes advantage of the thermal property of STT-MRAM, is proposed to reduce the LLC write energy. This policy splits the LLC into different regions dynamically based on the thermal distribution monitored by thermal sensors available on-chip, and adaptively migrates write intensive data among different thermal regions considering the thermal gradient. Compared to the conventional NUCA design, our proposed design can save 41.2% write energy at most and 13.01% on average with negligible hardware overhead.

中文翻译:

一种用于 STT-MRAM LLC 的新型高性能和节能 NUCA 架构,具有热考虑

随着现代处理器和片外主存储器的速度差距扩大,片上缓存容量增加以维持性能扩展。因此,缓存功率占据了总功率预算的很大一部分。由于其高集成密度和超低泄漏功率,自旋转移矩磁存储器 (STT-MRAM) 被提议作为低功耗缓存设计的有前途的解决方案。尽管如此,STT-MRAM 的高写入功率和延迟成为这项新兴技术商业化的新障碍。在本文中,我们研究了热效应对 STT-MRAM 访问性能的影响,并观察到温度会显着影响写入延迟和能量。然后,我们探索具有基于 STT-MRAM 的末级缓存 (LLC) 的芯片多处理器的非均匀缓存访问 (NUCA) 设计。提出了一种称为“Thermosiphon”的热感知数据迁移策略,它利用了 STT-MRAM 的热特性,以减少 LLC 写入能量。该策略根据芯片上可用的热传感器监测的热分布动态地将 LLC 划分为不同的区域,并在考虑热梯度的情况下自适应地在不同热区域之间迁移写入密集型数据。与传统的 NUCA 设计相比,我们提出的设计最多可节省 41.2% 的写入能量,平均可节省 13.01%,而硬件开销可忽略不计。该策略根据芯片上可用的热传感器监测的热分布动态地将 LLC 划分为不同的区域,并在考虑热梯度的情况下自适应地在不同热区域之间迁移写入密集型数据。与传统的 NUCA 设计相比,我们提出的设计最多可节省 41.2% 的写入能量,平均可节省 13.01%,而硬件开销可忽略不计。该策略根据芯片上可用的热传感器监测的热分布动态地将 LLC 划分为不同的区域,并在考虑热梯度的情况下自适应地在不同热区域之间迁移写入密集型数据。与传统的 NUCA 设计相比,我们提出的设计最多可节省 41.2% 的写入能量,平均可节省 13.01%,而硬件开销可忽略不计。
更新日期:2020-04-01
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