3-D triple-level cell (3-D TLC) NAND flash has high storage density and capacity, but degrading data reliability due to high raw bit error rates induced by a certain number of program/erase cycles. To guarantee data reliability, low-density parity-check (LDPC) codes are selected as the error correction codes in modern flash memories because of strong error correction capability. However, directly adopting LDPC codes induces high decoding latency due to iterative updating of log-likelihood ratio (LLR) information in the decoding process. Increasing LLR information accuracy can greatly improve decoding performance. In this paper, we propose EMAL: using error modes aware LDPC codes for further enhancing the decoding performance of 3-D TLC NAND flash. We first obtain 3-D TLC error modes based on an FPGA testing platform, and then exploit the error modes to optimize LLR information and enable the decoding to converge at a high speed. The simulation results show that the decoding performance is significantly improved, resulting in reduced bit error rates and decoding latency.

中文翻译：

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使用错误模式感知 LDPC 提高 3D TLC NAND 闪存的解码性能

3-D 三级单元 (3-D TLC) NAND 闪存具有高存储密度和容量，但由于一定数量的编程/擦除周期引起的高原始比特错误率导致数据可靠性降低。为了保证数据的可靠性，由于纠错能力强，现代闪存中选择低密度奇偶校验（LDPC）码作为纠错码。然而，由于在解码过程中对数似然比 (LLR) 信息的迭代更新，直接采用 LDPC 码会导致较高的解码延迟。提高 LLR 信息准确度可以大大提高解码性能。在本文中，我们提出了 EMAL：使用错误模式感知 LDPC 码来进一步增强 3-D TLC NAND 闪存的解码性能。我们首先基于 FPGA 测试平台获得 3-D TLC 错误模式，然后利用错误模式优化LLR信息并使解码高速收敛。仿真结果表明，解码性能显着提高，从而降低了误码率和解码延迟。