Ensuring the functional correctness of networks-on-chip (NoCs) can be particularly challenging, and communication-centric debug methodologies have been widely used by engineers to validate NoC functionality during post-silicon validation. Design-for-debug structures, such as trace buffers and monitors, are usually inserted in such systems-on-chip to enhance signal visibility. However, this debug hardware becomes underutilized once the chip goes into production. While the size and organization of the router buffers directly impact network throughput, these buffers also dominate the on-chip router area. We propose a scheme augmented virtual channel (AugVC) to reuse trace buffers to augment router buffers, with the objective of improving the overall network performance. The experimental results for a 64-node mesh network show that our proposed approach can reduce latency by up to 38.25% for transpose traffic compared to a baseline design with reduced buffer sizes. We also propose an extension, output port directed virtual channel (ODVC), that uses a modified virtual channel assignment strategy, on the basis of the designated output port of a network packet. This strategy reduces the average packet latency and area of the router by 45% and 32.4%, respectively.

中文翻译：

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通过重用跟踪缓冲区来增强片上网络性能

确保片上网络 (NoC) 的功能正确性可能特别具有挑战性，工程师已广泛使用以通信为中心的调试方法来在硅后验证期间验证 NoC 功能。为调试而设计的结构，例如跟踪缓冲器和监视器，通常被插入到这样的片上系统中以增强信号可见性。然而，一旦芯片投入生产，这种调试硬件就没有得到充分利用。虽然路由器缓冲区的大小和组织直接影响网络吞吐量，但这些缓冲区也支配着片上路由器区域。我们提出了一种增强虚拟通道（AugVC）方案来重用跟踪缓冲区来增强路由器缓冲区，目的是提高整体网络性能。64 节点网状网络的实验结果表明，与减少缓冲区大小的基线设计相比，我们提出的方法可以将转置流量的延迟减少多达 38.25%。我们还提出了一种扩展，即输出端口定向虚拟通道 (ODVC)，它基于网络数据包的指定输出端口，使用修改后的虚拟通道分配策略。该策略将路由器的平均数据包延迟和面积分别减少了 45% 和 32.4%。