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Low–Frequency Noise in Vertically Stacked Si n–Channel Nanosheet FETs
IEEE Electron Device Letters ( IF 4.1 ) Pub Date : 2020-03-01 , DOI: 10.1109/led.2020.2968093
Alberto V. de Oliveira , Anabela Veloso , Cor Claeys , Naoto Horiguchi , Eddy Simoen

This manuscript presents a systematic low–frequency noise analysis of inversion–mode vertically stacked silicon n–channel nanosheet MOSFETs on bulk wafers. Flicker noise due to carrier number fluctuations is shown as the dominant noise source, which is in line with previous reported studies on gate-all-around (GAA) nanowire nMOSFETs. In addition, the benchmark points out that the vertical stacking approach does not deteriorate the oxide trap density, since its normalized input–referred voltage noise Power Spectral Density at flat–band is lower compared to the data on non–stacked horizontal nanowire nMOSFETs. Another finding is that the Coulomb scattering mechanism dominates the mobility.

中文翻译:

垂直堆叠的 Si n 沟道纳米片 FET 中的低频噪声

本手稿对体晶片上的反转模式垂直堆叠硅 n 沟道纳米片 MOSFET 进行了系统的低频噪声分析。由于载流子数波动引起的闪烁噪声被显示为主要噪声源,这与之前报道的对环栅 (GAA) 纳米线 nMOSFET 的研究一致。此外,基准指出垂直堆叠方法不会降低氧化物陷阱密度,因为与非堆叠水平纳米线 nMOSFET 的数据相比,其归一化输入参考电压噪声功率谱密度在平带较低。另一个发现是库仑散射机制支配着迁移率。
更新日期:2020-03-01
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