This paper analyzes the absolute jitter performance of digital phase-locked loops and compares the case when either a multi-bit time-to-digital converter with mid-rise characteristic or a bang-bang phase detector is adopted. The linear equivalent model of the PLL and expressions for random-noise and limit-cycle jitter are first derived for the case of a 2-bit time-to-digital converter with a mid-rise characteristic, and the optimal TDC resolution is determined. The analysis, which account for TDC mismatches, shows that, compared to the 1-bit one, the 2-bit time-to-digital converter can substantially reduce the quantization noise in the case of dominant random-walk noise at the TDC input. Moving to the $N_{b}$ -bit midrise TDC case, the quantization noise can be further reduced at the cost of higher complexity and finer time resolution. The choice of $N_{b}=2$ seems to be the best compromise between jitter reduction and complexity increase. Time-domain simulations assess the theoretical framework and demonstrate the validity of the assumptions made throughout the paper.

中文翻译：

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具有中上升 TDC 的数字 PLL 中的抖动最小化

本文分析了数字锁相环的绝对抖动性能，并比较了采用具有中上升特性的多位时间数字转换器或采用bang-bang鉴相器的情况。首先推导出具有中间上升特性的 2 位时间数字转换器的 PLL 线性等效模型以及随机噪声和极限周期抖动的表达式，并确定最佳 TDC 分辨率。考虑到 TDC 失配的分析表明，与 1 位转换器相比，2 位时间数字转换器可以在 TDC 输入端随机游走噪声占主导地位的情况下显着降低量化噪声。搬到 $N_{b}$ -bit midrise TDC 情况下，量化噪声可以进一步降低，代价是更高的复杂性和更精细的时间分辨率。的选择 $N_{b}=2$ 似乎是减少抖动和增加复杂性之间的最佳折衷。时域模拟评估了理论框架并证明了整篇论文中所做假设的有效性。