First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches.

中文翻译：

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基于四重交叉耦合双互锁存储单元的多节点抗扰动锁存器设计

首先，本文提出了一种双节点翻转 (DNU) 完全容错 (DNUCT) 锁存器，具有四重交叉耦合双联锁存储单元 (DICE) 和 C 元件。由于存在足够的反馈回路，锁存器可以实现完全的 DNU 容忍。其次，本文提出了一种改进的 DNUCT 锁存器（称为 TNUCT 锁存器），通过在输出级插入冗余级别的 C 元素来拦截上游 DICE 中累积的节点翻转错误，从而完全容忍任何可能的三重节点翻转 (TNU)。仿真结果证明了所提出的锁存器的鲁棒性。由于使用了高速传输路径、时钟门控和更少的晶体管，这些创新的锁存器还具有成本效益。与可以完全容忍任何 TNU 的典型 TNU 硬化锁存器 (TNUHL) 设计相比，所提出的 TNUCT 锁存器将延迟功率面积乘积减少了大约 98%。与参考锁存器相比，所提出的锁存器对工艺、电压和温度变化的影响较小或相当。